Our research enables secure and sustainable scaling of computing systems. We tackle the security, sustainability, dependability, and performance challenges of modern and future systems across the system stack with a special focus on computer architecture. We help design fundamentally better systems leveraging security-oriented hardware-software co-design, data-centric security, and testing principles. In addition, our group is interested in building health-oriented systems with a focus on agent-based simulations and genome analysis.
Join the team! We are always looking for self-motivated people. Please fill out this application form to join us.
Computer architecture Hardware security Memory systems Dependability Hardware-Software Co-Design Data-Centric Security Testing and Verification
Team
Recent Collaborators
Onur Mutlu Ataberk Olgun Haocong Luo F. Nisa Bostancı İsmail Emir Yüksel Mohammad Sadrosadati Yahya Can Tuğrul Geraldo F. Oliveira Jeremie S. Kim Minesh Patel Oğuz Ergin Hasan Hassan Lois Orosa Oğuzhan Canpolat Juan Gómez-Luna Konstantinos Kanellopoulos Ismail Emir Yüksel Nisa Bostanci Steve Rhyner Jisung Park Saugata Ghose Andreas Kosmas Kakolyris Behzad Salami Daichi Tokuda Geraldo Francisco de Oliveira Harsh Songara Jawad Haj-Yahya Jikun Wang Joel Lindegger Konstantinos Marios Sgouras M. Banu Cavlak Majd Osseiran Melina Soysal Shinya Takamaeda-Yamazaki Taha Shahroodi Tatsuya Kubo Aditya Manglik Akash Sood Ataberk Olgun Carina Fiedler Daniel Gruss Efraim Rotem Fabrice Devaux Florian Adamsky Hannes Weissteiner Haocong Luo Ivan Puddu Joaquin Olivares Jonas Juffinger Kangqi Chen Kaveh Razavi Maria Makeenkova Martin Heckel Mayank Kabra Mohammed Alser Nandita Vijaykumar Nika Mansouri Ghiasi Nisa Bostanci Orhun Ecemis Patrick Jattke Rahul Bera Roknoddin Azizi Sudheendra Raghav Neela Tomoya Nagatani Ulrich Ruhrmair Umut Baser Yanos Sazeides Yu Liang Yuxin Guo Zülal BingolSelected Publications
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"Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller"in Proceedings of the 58th International Symposium on Microarchitecture (MICRO), Athens, Greece, 2026
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"ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems"in Proceedings of the 58th International Symposium on Microarchitecture (MICRO), Seoul, South Korea, 2025One of the 12 computer architecture papers of 2025 selected as Top Picks by IEEE Micro.
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"Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance"in Proceedings of the 31st International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, NV, USA, 2025Full Paper: [ pdf ] Slides: [ ppt ] [ pdf ] Artifact: [ code ] DRAMSec'24 Version: [ Paper ] [ Slides ppt ] [ Slides pdf ]Officially artifact evaluated as available, functional, and reproduced.Invited Talk at Future of Memory Systems (FMS) 2025Invited Talk at Hardwear.io, Amsterdam, 2025
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"Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions"in Proceedings of the 31st International Symposium on High-Performance Computer Architecture (HPCA), Las Vegas, NV, USA, 2025Officially artifact evaluated as available, functional, and reproduced.Distinguished Artifact Award at HPCA 2025
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"BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads"in Proceedings of the 57th International Symposium on Microarchitecture (MICRO), Austin, TX, USA, 2024Officially artifact evaluated as available, functional, and reproduced.Invited Talk at Hardwear.io, Amsterdam, 2025
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"ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation"in Proceedings of the 33rd USENIX Security Symposium (USENIX Security, Philadelphia, PA, USA, 2024Officially artifact evaluated as available, functional, and reproduced.
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"Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions"in Proceedings of the 30th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Edinburgh, United Kingdom, 2024
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"Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices"in Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Baltimore, MD, USA, 2022
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"A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses"in Proceedings of the 54th International Symposium on Microarchitecture (MICRO), Virtual, 2021
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"BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows"in Proceedings of the 27th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Virtual, 2021Paper: [ pdf ] Short Talk (7 mins): [ video ] [ ppt ] [ pdf ] Full Talk (22 mins): [ video ] [ ppt ] [ pdf ] Intel HWSec Academic Awards Talk (2 mins): [ video ] [ ppt ] [ pdf ]Intel Hardware Security Academic Award Finalist (one of 4 finalists out of 34 nominations)
Other Publications
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"Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding"in Proceedings of the 40th ACM International Conference on Supercomputing (ICS), Belfast, Northern Ireland (United Kingdom), 2026Preprint: [ pdf ]
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"PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems"in Proceedings of the ACM International Symposium on Computer Architecture (ISCA), Raleigh, North Carolina, USA, 2026Preprint: [ pdf ]
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"DeJaVu: Why You Should Write to Your DRAM Rows Twice, Carefully"in Proceedings of the ACM International Symposium on Computer Architecture (ISCA), Raleigh, North Carolina, USA, 2026Preprint: [ pdf ]
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"ScaleDisturb: Exploiting Temporal Asymmetry to Amplify Read Disturbance in Modern DRAM Chips"in Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Charlotte, North Carolina, USA, 2026Full Paper: [ pdf ]
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"Cleaning up the Mess: Re-evaluating the Real-System Modeling Accuracy of Ramulator 2.0"in Proceedings of the IEEE International Symposium on Performance Analysis of System and Software (ISPASS), Seoul, South Korea, 2026Preprint: [ pdf ]
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"Memory Band-Aid: A Principled RowHammer Defense-in-Depth"in Proceedings of the Network and Distributed System Security Symposium (NDSS), San Diego, CA, USA, 2026Preprint: [ pdf ]
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"Revisiting Main Memory-Based Covert and Side Channel Attacks in the Context of Processing-in-Memory"in Proceedings of the 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Naples, Italy, 2025Officially artifact evaluated as available, reviewed, and reproduced.
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"Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems"IEEE Access, 2024
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"Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture"ACM Transactions on Architecture and Code Optimization (TACO), 2024
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"RowPress Vulnerability in Modern DRAM Chips"Special Issue, IEEE Micro, Special Issue: Micro's Top Picks from 2023 Computer Architecture Conferences (MICRO TOP PICKS), 2024Full Paper: [ pdf ]
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"Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips"in Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Brisbane, Australia, 2024Officially artifact evaluated as both code and dataset available, reviewed and reproducible.
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"Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis"in Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Brisbane, Australia, 2024Officially artifact evaluated as both code and dataset available, reviewed and reproducible.
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"An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips"in Proceedings of the 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Disrupt Track (DSN Disrupt), Brisbane, Australia, 2024
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"CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost"in Proceedings of the 30th International Symposium on High-Performance Computer Architecture (HPCA), Edinburgh, UK, 2024Officially artifact evaluated as available, functional, and reproduced.
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"MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing"in Proceedings of the 30th International Symposium on High-Performance Computer Architecture (HPCA), Edinburgh, UK, 2024
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"SpyHammer: Understanding and Exploiting RowHammer Under Fine-Grained Temperature Variations"IEEE Access, 2024Full Paper: [ pdf ]
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"RowPress: Amplifying Read Disturbance in Modern DRAM Chips"in Proceedings of the 50th International Symposium on Computer Architecture (ISCA), Orlando, FL, USA, 2023Full Paper: [ pdf ] Extended Version: [ pdf ] Lightning Talk (3 mins): [ video ] [ ppt ] [ pdf ] Full Talk (26 mins): [ video ] [ ppt ] [ pdf ] Source Code: [ code ]Officially artifact evaluated as available, reusable and reproducible.Distinguished artifact award at ISCA 2023.One of the 12 computer architecture papers of 2023 selected as Top Picks by IEEE Micro.
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"QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips"in Proceedings of the 48th International Symposium on Computer Architecture (ISCA), Virtual, 2021
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"Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques"in Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, 2020
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"EDEN: Energy-Efficient, High-Performance Neural Network Inference Using Approximate DRAM"in Proceedings of the 52nd International Symposium on Microarchitecture (MICRO), Columbus, OH, USA, 2019
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"CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability"in Proceedings of the 46th International Symposium on Computer Architecture (ISCA), Phoenix, AZ, USA, 2019
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"What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study"in Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Irvine, CA, USA, 2018
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"Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms"in Proceedings of the ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Urbana-Champaign, IL, USA, 2017
Technical Reports
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"Security Analysis of the Silver Bullet Technique for RowHammer Prevention"arXiv:2106.07084 [cs.CR], 2021Full Paper: [ pdf ]